The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to reducing minimum operating voltage through a hybrid cache design.
With the scaling of transistor dimensions, variability in the number and location of channel dopant atoms may result in restrictive electrical deviations in the device threshold voltage. These fluctuations can generally be most prominent in minimum geometry devices, which may be used in area-limited circuits such as 6T (six-transistor) SRAM (Static Random Access Memory) cell. The mismatch in the threshold voltage between neighboring transistors within an SRAM cell may dramatically reduce the cell stability during a read or write operation. Read stability generally refers to the ability of a cell to retain its contents during a read operation while considering device mismatch. Write stability generally refers to the ability to write a cell while considering device mismatch. Further, retention stability is generally the ability of a cell to retain states during standby mode (e.g., where operating voltage is reduced but not completely turned off). To be considered stable, an SRAM cell needs be designed to meet a minimum cell stability requirement set to minimize the number of defect dies. Process scaling may make it harder to meet this requirement, since device parameter variations may become worse.
Generally, SRAM stability may dramatically degrade with the scaling of supply voltage (Vcc), needed for low-power designs. For example, in some cases, only tens of bits may fail out of millions during operation at a lower voltage, but those failing bits may determine the supply voltage level at which the entire SRAM (and other logic on the same integrated circuit (IC)) may operate, thus wasting power by operating the remaining (majority of) cells at an unnecessarily higher voltage.
Some current designs attempt to solve the stability problem through the use of a higher separate supply voltage for SRAM cells which does not scale with Vcc. Some of the drawbacks of such a scheme are extra supply generation and distribution, level shifter for data interfaces, and power management.
Accordingly, memory cell stability (such as cache memory cell stability) may be a major concern with process and supply voltage scaling.